Counterintuitive memory setting

[jaeger]

Nifty little trick for those overclockers out there.

Originally had my t(ras) setting at 5 which was the lowest my mem would support, and I thought that would also be the fastest setting. After reading a guide, I set the t(ras) to 11. Booted into windows fine and better bandwidth. Went back and was able to overclock the FSB another 4 Mhz. All perfectly stable. So setting t(ras) to 11 netted me 100 MB/sec mem bandwidth and another 50 mhz headroom on my cpu. Apparently the optimal t(ras) setting varies with fsb, for 200 Mhz 11 appears best. The lower the fsb, the lower the optimal t(ras).

Worth noting, I'm running an 8rda+ rev 1.1 with hyperx pc3000 memory. YMMV with other chipsets.

[confus-ed]

Originally posted by jaeger
...Originally had my t(ras) setting at 5 which was the lowest my mem would support, and I thought that would also be the fastest setting....

"Counterintuitive" .... my that is a long word for WD ... :D

If you were as old as I you'd have learn't about core store ! then you'd realise that the faster the computer goes, the less often in any cycle memory requires refresh in terms of t - ticks, all any piece of memory is, is a little iddy biddy elctro magnet that decays with time & requires refreshing - ras & cas timings do that, vertical & horizontal refresh of cores in an array repressenting phsical memory within each chip.

So the faster the machine goes the less frequently in any cycle you need to refresh memory as the rate of decay is a constant value ...

So it might be 'Counterintuitive' to you but it makes complete sense to me ... faster isn't always better .... ;)

[Outcoded]

You are showing your age confus-ed. SD-RAM doesn't need to refresh - it's static.

[confus-ed]

Originally posted by Outcoded
You are showing your age confus-ed. SD-RAM doesn't need to refresh - it's static.

Isn't that SRAM (http://www.webopedia.com/TERM/S/SRAM.html) ? Don't get me any more confus-ed than I am ... ;)

SDRAM: Synchronous DRAM. Operates in sync with the CPU clock to avoid the delays caused by asynchronous operation

Neither of us would be banging on about cas timings if it were static !