TechZ
March 23rd, 2007, 03:16 PM
Boffins working for the US military contractor Raytheon have come up with what they are computers that can adopt different forms depending on what they have to run. Called, Monarch (Morphable Networked Micro-Architecture) the computer has been developed (http://www.mil-embedded.com/news/db/?5784) to tackle the large data volume of sensor systems as well as their signal and data processing throughput requirements. It performs as a single system on a chip, resulting in a significant reduction of the number of processors required for computing systems, and it performs in an array of chips for teraflop throughput. In addition to the ability to adapt its architecture for a particular objective, the MONARCH computer is also believed to be the most power- efficient processor available. The company has begun tests on prototypes of the polymorphic MONARCH processors to verify they'll function as designed and to establish their maximum throughput and power efficiency. MONARCH, containing six microprocessors and a highly interconnected reconfigurable computing array, provides 64 gigaflops (floating point operations per second) with more than 60 gigabytes per second of memory bandwidth and more than 43 gigabytes per second of off-chip data bandwidth.
The MONARCH processor was developed under a Defense Advanced Research Project Agency (DARPA) polymorphous computing architecture contract from the U.S. Air Force Research Laboratory. Raytheon Space and Airborne Systems led an industry team with the Information Sciences Institute of the University of Southern California to create the integrated large-scale system on a chip with a suite of software development tools for programs of high value to the Department of Defense and commercial applications. Besides USC major subcontractors included Georgia Institute of Technology, Mercury Computer Systems and IBM's Global Engineering Solutions division.
The MONARCH processor was developed under a Defense Advanced Research Project Agency (DARPA) polymorphous computing architecture contract from the U.S. Air Force Research Laboratory. Raytheon Space and Airborne Systems led an industry team with the Information Sciences Institute of the University of Southern California to create the integrated large-scale system on a chip with a suite of software development tools for programs of high value to the Department of Defense and commercial applications. Besides USC major subcontractors included Georgia Institute of Technology, Mercury Computer Systems and IBM's Global Engineering Solutions division.